#include "../include/ddr_common_func.h"
#include "../include/pinmux.h"

void dq_pinmux (enum DDR_BITWIDTH bits) {
ddr_phy_broadcast_en(0);    

ddr_phy0_reg_wr(0x100a0,0x1);
ddr_phy0_reg_wr(0x100a1,0x5);
ddr_phy0_reg_wr(0x100a2,0x3);
ddr_phy0_reg_wr(0x100a3,0x0);
ddr_phy0_reg_wr(0x100a4,0x2);
ddr_phy0_reg_wr(0x100a5,0x4);
ddr_phy0_reg_wr(0x100a6,0x6);
ddr_phy0_reg_wr(0x100a7,0x7);
//PHY0 DBYTE1
ddr_phy0_reg_wr(0x110a0,0x7);
ddr_phy0_reg_wr(0x110a1,0x4);
ddr_phy0_reg_wr(0x110a2,0x3);
ddr_phy0_reg_wr(0x110a3,0x0);
ddr_phy0_reg_wr(0x110a4,0x2);
ddr_phy0_reg_wr(0x110a5,0x1);
ddr_phy0_reg_wr(0x110a6,0x5);
ddr_phy0_reg_wr(0x110a7,0x6);
//PHY0 DBYTE2
ddr_phy0_reg_wr(0x120a0,0x7);
ddr_phy0_reg_wr(0x120a1,0x4);
ddr_phy0_reg_wr(0x120a2,0x3);
ddr_phy0_reg_wr(0x120a3,0x0);
ddr_phy0_reg_wr(0x120a4,0x2);// FullMask version
ddr_phy0_reg_wr(0x120a5,0x1);// FullMask version
ddr_phy0_reg_wr(0x120a6,0x5);
ddr_phy0_reg_wr(0x120a7,0x6);
//PHY0 DBYTE3
ddr_phy0_reg_wr(0x130a0,0x7);
ddr_phy0_reg_wr(0x130a1,0x5);
ddr_phy0_reg_wr(0x130a2,0x0);
ddr_phy0_reg_wr(0x130a3,0x2);
ddr_phy0_reg_wr(0x130a4,0x1);
ddr_phy0_reg_wr(0x130a5,0x4);
ddr_phy0_reg_wr(0x130a6,0x3);
ddr_phy0_reg_wr(0x130a7,0x6);
if(bits==DDR_BITWIDTH_64) {
//PHY1 DBYTE0
ddr_phy1_reg_wr(0x100a0,0x7);
ddr_phy1_reg_wr(0x100a1,0x4);
ddr_phy1_reg_wr(0x100a2,0x3);
ddr_phy1_reg_wr(0x100a3,0x0);
ddr_phy1_reg_wr(0x100a4,0x1);
ddr_phy1_reg_wr(0x100a5,0x2);
ddr_phy1_reg_wr(0x100a6,0x5);
ddr_phy1_reg_wr(0x100a7,0x6);
//PHY1 DBYTE1
ddr_phy1_reg_wr(0x110a0,0x7);
ddr_phy1_reg_wr(0x110a1,0x5);
ddr_phy1_reg_wr(0x110a2,0x0);
ddr_phy1_reg_wr(0x110a3,0x2);
ddr_phy1_reg_wr(0x110a4,0x1);
ddr_phy1_reg_wr(0x110a5,0x4);
ddr_phy1_reg_wr(0x110a6,0x3);
ddr_phy1_reg_wr(0x110a7,0x6);
//PHY1 DBYTE2
ddr_phy1_reg_wr(0x120a0,0x1);
ddr_phy1_reg_wr(0x120a1,0x5);
ddr_phy1_reg_wr(0x120a2,0x3);
ddr_phy1_reg_wr(0x120a3,0x0);
ddr_phy1_reg_wr(0x120a4,0x2);
ddr_phy1_reg_wr(0x120a5,0x4);
ddr_phy1_reg_wr(0x120a6,0x6);
ddr_phy1_reg_wr(0x120a7,0x7);
//PHY1 DBYTE3
ddr_phy1_reg_wr(0x130a0,0x7);
ddr_phy1_reg_wr(0x130a1,0x4);
ddr_phy1_reg_wr(0x130a2,0x3);
ddr_phy1_reg_wr(0x130a3,0x0);
ddr_phy1_reg_wr(0x130a4,0x2);
ddr_phy1_reg_wr(0x130a5,0x1);
ddr_phy1_reg_wr(0x130a6,0x5);
ddr_phy1_reg_wr(0x130a7,0x6);

ddr_phy_broadcast_en(1);    
}

}
